1. Field of the Invention
Embodiments of the present invention generally relate photomasks used in the fabrication of semiconductor devices, more specifically, to a photomask having a self-masking layer and methods of etching thereof.
2. Description of the Related Art
In the manufacture of integrated circuits (IC), or chips, patterns representing different layers of the chip are created by a chip designer. A series of reusable photomasks (also referred to herein as masks) are created from these patterns in order to transfer the design of each chip layer onto a semiconductor substrate during the manufacturing process. Mask pattern generation systems use precision lasers or electron beams to image the design of each layer of the chip onto a respective mask. The masks are then used much like photographic negatives to transfer the circuit patterns for each layer onto a semiconductor substrate. These layers are built up using a sequence of processes and translate into the tiny transistors and electrical circuits that comprise each completed chip. Thus, any defects in the mask may be transferred to the chip, potentially adversely affecting performance. Defects that are severe enough may render the mask completely useless. Typically, a set of 15 to 30 masks is used to construct a chip and can be used repeatedly.
A mask generally comprises a transparent substrate having an opaque, light-absorbing layer disposed thereon. Conventionally, the mask is typically a glass or a quartz substrate that has a layer of chromium on one side. The chromium layer is covered with an anti-reflective coating and a photosensitive resist. During a patterning process, the circuit design is written onto the mask by exposing portions of the resist to an electron beam or ultraviolet light, making the exposed portions soluble in a developing solution. The soluble portion of the resist is then removed, allowing the exposed underlying chromium to be etched. The etch process removes the chromium and anti-reflective layers from the mask at locations where the resist was removed, i.e., the exposed chromium is removed.
Key challenges of mask fabrication include etch critical dimension (CD) bias control, etch CD uniformity, cross sectional profiles, etch CD linearity, etch selectivity, and defectivity control. However, with the shrinking of critical dimensions of the mask (corresponding to the shrinking dimensions of the transistors and electrical circuits formed in the ICs), present optical lithography techniques are approaching their technological limit. For example, for current optical binary mask, etch CD bias for a conventional mask under a 65 nm type process is about 15-20 nm on a state-of-art mask etcher. This etch bias issue mainly results from erosion of photoresist. During pattern transfer, the photoresist is consumed significantly because of the limited etch rate selectivity of the absorber layer to the photoresist. This consumption of photoresist lowers the fidelity of the pattern transfer process.
Thus, there is a need for an improved mask and mask fabrication methods.